This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-327370, filed on Oct. 25, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a delay circuit. Especially, the present invention relates to a delay circuit implemented on a semiconductor integrated circuit.
2. Related Background Art
The delay circuit on the semiconductor integrated circuit is composed of inverters and the other logic gates. FIG. 9 is a circuit diagram of a conventional variable delay circuit capable of adjusting the delay amount. The variable delay circuit of FIG. 9 adjusts delay time by the number of stages that an input signal IN passes through NAND gates and inverters. NAND gates G14, G15 and G16 are connected to one of input terminals of the NAND gates G11, G12 and G13 connected in series, respectively. An input signal IN is commonly inputted to one input ends of the NAND G14, G15 and G16. Delay selection signals SEL less than 0 greater than , SEL less than 1 greater than  and SEL less than 2 greater than  are inputted to the other input ends of the NAND gates G14, G15 and G16, respectively.
In the variable delay circuit of FIG. 9, when the delay selection signal SEL less than 0 greater than , SEL less than 1 greater than  and SEL less than 2 greater than  are set to be in low, high and low, respectively, the input signal is propagated along arrows of FIG. 9B. When the delay selection signals SEL less than 0 greater than , SEL less than 1 greater than  and SEL less than 2 greater than  are set to be in low, low and high, respectively, the input signal is propagated along the arrows of FIG. 9B.
Thus, when only one of the delay selection signals SEL less than 0 greater than , SEL less than 1 greater than  and SEL less than 2 greater than  is set to be in high level, the number of stages of the gates on the signal propagation path from the input IN to the output OUT changes. As a result, it is possible to adjust the delay time from the input IN to the output OUT.
However, in the variable delay circuit of FIG. 9, when the delay selection signal is switched, the number of stages of the gates that the input signal IN passes through changes two stages at the minimum. That is, the variable delay circuit of FIG. 9 cannot adjust the delay time in units of less than two stages of the gates.
Recently, operational frequency of various semiconductor integrated circuits including a CPU becomes higher. In accordance with speeding-up of the operational frequency of the semiconductor integrated circuits, it is desirable to be able to adjust the delay time of various signals in minute units. If the delay time cannot be adjusted in units of less than two stages of the gates, it is impossible to improve accuracy of the delay time.
A delay circuit according to one embodiment of the present invention, comprising:
a plurality of delay blocks connected in series, each having a first complementary input terminal to which a first complementary signal is inputted, a second complementary input terminal to which a second complementary signal is inputted, and a complementary output terminal which outputs a third complementary signal delaying by selecting one of said first and second complementary signals based on logic of a delay selection signal,
said complementary output terminal of said delay blocks except for said delay block of last stage being connected to said second complementary input terminal of the subsequent delay block, respectively,
a complementary delay signal delaying said first complementary signal in accordance with logic of said delay selection signal being outputted from said complementary output terminal of said delay block of last stage, and
the same first complementary signal is inputted to said first complementary input terminals of said plurality of delay blocks, respectively.